An analog signal is a continuously variable quantity; it has a value at all times and has amplitude that is continuous. A digital approximation to an analog signal is conventionally made by generating a sequence of quantized number (numbers with a finite resolution) each the closest approximation to the analog quantity at regular intervals in time. For example, the digitization of audio signals by a CD player is accomplished by taking samples of so-called “16 bit resolution” at a regular rate of 44.1 Khz. “16 bit resolution” implies that the digital representation of the amplitude is over 16 binary bits and so accurate to about 1/65536 or approximately 16 ppm (parts per million). Another example is the digital audio that is reordered on a DVD disk. In this case the samples of amplitude may be resolved to 24 bits or about 0.06 ppm and the regular rate of taking these samples is at 48 Khz. Therefore, in the audio consumer applications we have at least two different sample rates (44.1 khz and 48 khz) and two different amplitude resolutions (16 and 24 bits) commonly used. FIG. 1A shows an example: here SIGNAL1 is sampled at 44.1 khz and results in the sequence of points marked by the “x”. SIGNAL 2 is sampled at a higher rate (48 khz) and results in the sequence of points marked by “o”.
The existence of two sampling rates within a system can be inconvenient: consider the case where a stream of digital audio data is arriving from a DVD source at 48 khz and a second stream at 44.1 khz is arriving from an ADC and a microphone source (this situation occurs when a “karaoke” player is using a DVD as a backing instrumental and the ADC is encoding the singer). How shall these two signals be mixed and output through the same audio output device? This is a problem because the input samples are arriving at different times—if the 48 khz source is used to run the digital signal processor (or, more precisely, if the DSP is configured to operate on samples at 48 khz) the samples of the 44.1 khz signal arrive in between the 48 khz samples—they must be delayed or otherwise approximated into the regular rate of the 48 khz in order to processed together. This is the “asynchronous sample rate” conversion problem and this disclosure teaches how samples of a signal arriving asynchronously with relation to some chosen clock can be approximated as a sample at that clock: the asynchronous samples are converted to synchronous samples in a given clock domain that nevertheless accurately represent the signal as it was sampled in the original (now asynchronous relative to the new clock) domain.
It is a requirement of this invention that the chosen clock be at a rate substantially greater than the input sample rate. FIG. 1B shows how a sequence of samples at 44.1 khz may be approximated into a much higher clock rate be performing a “zero order hold” function.
A “zero order hold” function is simply the repetition of the last sample that was seen by the higher speed clock. Note that in FIG. 1B the samples at 44.1 khz do not in general fall at the same time as any of the samples at the higher clock rate. The higher clock rate samples are repetitions of the sample last seen in the 44.1 khz domain. Therefore there is an error: as shown in FIG. 2D—the input sample changed slightly before the first changed sample in the higher clock domain.
Referring to FIG. 1, a sample analog input signal operating at a frequency “f” is illustrated. In common practice, samples of the signal are taken at sample points, where the number of samples, n, determines the accuracy of the sample. The higher the number of samples, the more accurate reading of the analog signal can be taken. Thus, the frequency of samples taken is much higher than the frequency of the incoming signal. For example, referring to FIG. 2A, if the incoming signal 202 was operating at 44.1 kHz, the data sample points 204 may be taken at 27 MHz.
Errors, however, occur when trying to predict the exact value of a signal at a point. The latency in a circuit that samples the data can cause errors in reading the signal. Sample point 206, for example, is taken in series with previous samples. Sample 208, however is at a transition point, where the next sample, 210 is read at the half way point, then sample 212 is read subsequently, followed by sample points 214 and 216. Continuing, sample point 218 is taken, then sample point 220 is at another transition point. Conventional circuits read point 222, followed by 224 and 226. The actual points from the ideal, however, are corner points 228 and 230. Again, the latency in the circuitry causes artifacts such as these to occur, and for signals to be read in the midst of errors. In conventional systems, an input system would over sample the input to pinpoint f(in), input frequency. This method, however, is inaccurate, and requires expensive circuitry to take more accurate samples.
Referring to FIG. 2B, an illustration of input points and output clock points are compared. As can be seen, the output clock points occur after the corresponding input points. Thus, they are at different frequencies. Referring to FIG. 2C, an illustration of a digitized signal is shown, where the x's correspond to the actual input at the input clock. The o's correspond to the correct output clock points. Ideally, the o's will correspond to the output clock signal points. In conventional systems that use synchronous clocks, this is not possible, and signal artifacts result.
Accordingly, there exists a need in the art for a system and method for more accurate sampling of signals, correcting for common artifacts. As will be seen, the invention accomplishes this in an elegant manner.